View the profiles of people named Laurent Souef. Join Facebook to connect with Laurent Souef and others you may know. Facebook gives people the power to. Semantic Scholar profile for Laurent Souef, with fewer than 50 highly influential citations. Family tree Laurent Souef.

Author: Fenrizilkree Yozshukree
Country: Fiji
Language: English (Spanish)
Genre: Travel
Published (Last): 28 August 2009
Pages: 258
PDF File Size: 12.96 Mb
ePub File Size: 6.44 Mb
ISBN: 704-6-76080-942-3
Downloads: 2948
Price: Free* [*Free Regsitration Required]
Uploader: Kajilkis

Jerome Bombal, Laurent Souef. Design for test area optimization algorithm. Each of the stages or cells comprises a flip-flop and a multiplexer which together operate as a toggle flip-flop only ssouef all of the previous flip-flops are set.

BibTeX records: Laurent Souef

The present invention, generally speaking, provides an laursnt circuit testing technique in which hardware accessibility of selected components is exploited sokef order to avoid scan insertion overhead but achieve as good or better fault coverage than if scan insertion had been used.

The term “pseudo-scan” is used to refer to the use of read and write instructions to lauretn the equivalent effect as scan insertion without the addition of scan flops. Pseudo-scan testing using hardware-accessible IC structures. The test program extracts the simulated scan flops and graphically displays the simulated scan flops versus time.

The memory is configured to provide a database, and is operative to store a netlist including nets of an integrated circuit under design. These means for setting the output voltage are controlled by a control signal 15 which depends on the mode signal that indicates whether the signal is in the test mode or in the operation mode.

Laurent Souef

Each cluster of switches ; lxurent a first switch having a first size and a second switch having a second size, a fault-free first switch having a higher resistance than a fault-free second switch Cell with fixed output voltage for integrated circuit. The result is that the flip-flop clock is forced high preventing any transition of the flip-flop internal clock tree for all stages or cells where the output is low. The IC further comprises a test arrangement for testing the respective clusters of switches ; in a test mode.

Laurent Souef, Didier Gayraud. A key handling circuit for a switching matrix having laudent and column conductors includes bidirectional drives for the row conductors and the column conductors.


The test vector bits are passed between adjacent portions of the shift register arrangement timed with the first clock signal 42 and an output response laurfnt the integrated circuit to the test vector is provided and analyzed.

Low power scannable counter. In an integrated suoef incorporating a series of sequential cells SEQ 1 -SEQ 7 implementing a shift function, clock skew problems are avoided by interconnecting the cells in order starting with the cell SEQ 3 having greatest clock latency and ending with the cell SEQ 7 having smallest clock latency.

Laurent Souef Inventions, Patents and Patent Applications – Justia Patents Search

The row laursnt provides a current input for the column drive in one phase of operation and the column drive wouef a current input for a row drive in a second phase of operation.

Laurent Souef, Emmanuel Alie. An integrated circuit is disclosed comprising a plurality of circuit portionseach of the circuit portions having an internal supply rail coupled to a global supply rail via a cluster of switches ; coupled in parallel between the internal supply rail and the global supply rail The output response of the integrated circuit to the test vector is provided under the control of a second clock signal 56 which is slower than the first clock signal.

A low power scannable asynchronous counter which is fully testable and which consumes low power in a functional mode consists of counter cells cascaded through NOR gate circuits to which clock signals are applied for each of the stages or cells. Koninklijke Philips Electronics N.

Method of discriminating between different types of scan failures, computer readable code to cause a display to graphically depict one or more simulated scan output data sets versus time and a computer implemented circuit simulation and fault detection system.

Thus, no power consumption of such stages takes place during functional operation. A method of testing an integrated circuit, comprises soouef a test vector to a shift register arrangement by providing test vector bits in series into the shift register arrangement 20 timed with a first, scan, clock signal Frederic Natali, Laurent Souef.

Existing ATPG tools may be used without modification by performing scan insertion on a “dummy” circuit and performing ATPG on the scan-augmented dummy circuit. Laurent Souef has filed for patents to protect the following inventions. The resulting ATPG vectors are then modified to perform pseudo scan of selected components of the original circuit.


Method of testing an integrated circuit by simulation.

dblp: Laurent Souef

This testing method speeds up the process by increasing the speed of shifting test vectors and results into and out of the shift register, but without comprising the stability of the testing process. A method of discriminating between different types sohef simulated scan failures includes simulating a scan enable signal to a circuit represented by a netlist corresponding to a scan chain coupled to combinatorial logic being tested, simulating initiation of a data capture cycle in the netlist corresponding to the scan chain, the data capture cycle simulating a laureny of scan flops from the scan chain being simulated together with the combinatorial logic and simulating scanning data out from each flop in the scan chain and into a test program.

Patrick Laueent Silva, Laurent Souef. The test arrangement comprises a test control input; a test output coupled to the respective internal supply rails and control means, coupled to the test control input for enabling a selected cluster of switches ; in the test mode.

The invention relates to a testable integrated circuit. The automatic test pattern generation ATPG algorithm is operative to design and test an integrated circuit design.

Clock-skew resistant chain of sequential cells. In the scan test mode, the counter operates as sojef shift register and it is fully testable.

Furthermore, the method can be implemented without requiring additional complexity of the testing circuitry to be integrated onto the circuit substrate. Computer implemented circuit synthesis lauent. The row drive and the column drive are in a low conductive condition except when a relevant key switch is activated.

A computer implemented circuit synthesis system includes a memory, an automatic test pattern generation ATPG algorithm, and processing circuitry. In order to replace ground and VDD in certain points of such a circuit, the circuit comprises a cell 34 which comprises a flipflop 11 and means 31 able to set the output voltage of the cell when the circuit is in the operation mode.